A single-phase seven-level ANPC inverter with hybrid modulation for enhanced efficiency and harmonic performance | Scientific Reports

Scientific Reports volume 15, Article number: 9551 (2025) Cite this article

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Switched-capacitor (SC) multilevel inverters (MLIs) are widely used in a variety of applications due to their ability to boost voltage and balance capacitor voltage. High efficiency inverters with high boosting leads to inverters with higher component count and lower efficiency. This article proposes a seven-level active neutral point clamped-based SC inverter with a boosting of 1.5. The proposed topology, which includes six switches, and six diodes, produces a seven-level output voltage with an efficiency of 98.4%, and voltage and current THD% of 22.27% and 10.67%. This article also suggests integrating Level Shifted (LS) PWM with Phase Shifted (PS) PWM. The amalgamation enhances the converter’s overall efficiency by lowering switching losses by combining the benefits of both switching technologies. The reliability of the proposed inverter has also been analysed. The simulation as well as hardware results have been presented to validate the performance of the proposed inverter.

The increasing popularity of photovoltaic (PV) energy generation systems can be attributed to their quiet and environmentally friendly operation, in addition to the inexhaustible availability of solar energy. Since the voltage produced by solar PV, hence, power electronic converters are of utmost importance in PV-based power systems, where widely used components include inverters and DC-DC converters. Contemporary times are critical for power electronics-based conversion systems, as they facilitate the dependable and efficient utilization of renewable energy sources1. Multiple decades have been devoted to investigating and advancing multilevel inverters (MLIs). Renewable energy sources (RES) and their ability to function effectively in industrial environments are gaining recognition for their value2. Most notably, MLIs are utilized extensively due to their adaptability to various circumstances, lower dv/dt, reduced filtering requirements, and lower device voltage stress. These advantageous attributes of MLIs enable them to be the preferred choice for various applications such as in renewable energy sources (RES), uninterruptible power supply (UPS) systems, motor drive applications, electric vehicles, and more3. Notably, MLIs find prominent use in harnessing power from RESs. Traditional MLIs include topologies like the cascaded H-bridge, the flying capacitor, and the diode-clamped. Due to the practical limitation imposed by the clamping diodes, diode-clamped MLIs find limited use in high-level applications4. The flying capacitor multilevel inverter uses capacitors for voltage clamping instead of diodes, making it similar to the diode-clamped MLI. As the number of output voltage levels increases, the structure and regulation evolve more complicated in an inversely proportionate manner. Novel MLI designs are being developed that require fewer components5.

Switched capacitor-based multilevel inverters (SC-MLIs) have gained popularity to increase output voltage levels while simplifying the system, according to recent research. The ability to boost voltage and the automatic self-voltage balancing of their capacitors are two features that set SC-MLIs apart6. Because the capacitors are connected in series with the DC source and charged in parallel with the source, they are set up to discharge and charge at different times during a fundamental cycle. But as the number of desired output voltage levels rises, more capacitors and semiconductor devices are needed. There are several compelling benefits associated with switched capacitor multilevel inverters (SC-MLIs)7. Moreover, SCMLIs can boost voltage levels as needed, making them versatile in applications where higher voltage outputs are necessary. These inverters are known for their efficiency, scalability, and suitability for high-power and high-voltage applications, such as electric vehicles, renewable energy systems, and industrial drives. Their flexibility in adapting to varying voltage requirements adds to their appeal, making SC-MLIs a valuable choice for modern power conversion needs8.

Researchers have used level-shifted and phase-shifted modulation techniques commonly for controlling SC-MLIs. Level shift modulation approach involves shifting the voltage levels of the output waveforms to generate the desired AC output voltage9. Level shift modulation changes the switching patterns of semiconductor devices so that the output voltage can be controlled very precisely. This makes it an important part of converting power in many situations, like motor drives and renewable energy systems. Multilevel Inverters (MLIs) are additionally regulated using the LS-PWM technique, which encompasses several methods such as Phase-Opposed Disposed (POD) PWM, Phase-Disposed (PD) PWM, and Alternate POD (APOD) PWM. However, applying LS-PWM to Current-Source Multilevel Inverters (CMIs) reveals an inherent disadvantage10. It has been pointed out that this PWM method causes uneven power distribution among the active modules, which means it is not suitable to be used in photovoltaic (PV) systems. Phase shift modulation changes the timing and phase relationships between switching devices and makes multilevel waveforms with certain frequencies and voltage levels. This level of control is essential for optimizing the performance and efficiency of power conversion systems, particularly in industries like renewable energy, where power quality and grid integration are paramount11.

Recently, research has been devoted to the examination of hybrid modulation methods that integrate phase shift and level shift modulation. In contrast to employing either of the modulation techniques in isolation, these hybrid approaches have demonstrated superior dependability and efficacy. In numerous power electronics applications, these hybrid approaches enhance efficiency, effectiveness, and power quality by incorporating the advantages of phase and level shift modulation. Their significance in advancing the discipline is proven by this. One of the hybrid techniques, also named 'Hybrid-PWM, is a PWM technique possessing the benefits of both Level shifted and Phase shifted modulation. Hybrid Pulse Width Modulation (H-PWM) is a carrier-based PWM method. This technique incorporates the combined benefits and characteristics of both LS-PWM and PS-PWM12. In a previous study, the PS Pulse width Amplitude Modulation (PS-PWAM) was introduced, which achieves optimal semiconductor switching but sacrifices modularity12. Different switches operating at various times within a module are the cause of different frequencies. This means that a bigger heat sink had to be chosen. Additionally, the process of generating switching pulses becomes exceedingly intricate and is unsuitable for a larger number of modules.

In this work, a novel hybrid of LS-PWM and PS-PWM is proposed. The most significant benefit achieved by the proposed technique is the optimum loss in consideration of switching and conduction losses. In LS-PWM, although the switching losses are low, conduction losses are higher, whereas for the PS-PWM the conduction losses are lower than the proposed, but the switching losses are significantly high and reduced to a good extent, thus overall efficiency is improved to comparison to both modulation techniques.

Features of this article include:

Proposing a SCMLI topology generating seven levels for grid applications with improved efficiency.

The hybrid of LS-PWM and PS-PWM proposed takes the best parts of both modulation techniques and puts them together. This makes the system more efficient and cuts down on switching losses.

Enhanced efficiency.

This section discusses the proposed topology and its operation principle.

The proposed inverter shown in Fig. 1 consists of six switches, four capacitors, and six diodes. Diodes 3,4,5, and 6 together with Sb5 make it a bidirectional switch. It has four switch legs: one of which has one bidirectional switch- Sb6, two of the switch legs consist of two switches each—S1 and S2, S3 and S4. The fourth switch leg consists of one switch and four diodes making a bidirectional switch- Sb5. It’s one end is connected to the neutral point whereas the other end is connected between S3 and S4. Sb6’s one end is connected to the neutral while the other is connected between S1 and S2. The maximum attainable voltage is 3/2 Vdc. The proposed inverter also utilizes a small inductor at the charging path of capacitors to the suppress the inrush charging current13. The proposed modulation scheme in section "Proposed hybrid modulation technique" also ensures that the charging current is within limits. It can be seen in Figs. 20 and 21 in section "Simulation and experimental results", that the proposed modulation scheme when implemented on the proposed topology results in comparatively lower charging current when compared with LS-PWM and PS-PWM.

Proposed inverter-seven level.

When used in medium voltage systems, switched capacitor multilevel inverters (SCMLI) have a number of drawbacks. The higher switching losses brought on by the numerous cycles of capacitor charging and discharging are one of the main problems. These losses can have a major effect on overall efficiency and heat generation in medium voltage applications where the inverter must react rapidly to changes in load or operating circumstances. Furthermore, the more capacitors there are, the more difficult it is to balance the voltage between them, which results in an unequal distribution of charge. This imbalance may lead to performance deterioration or capacitor failure, affecting the inverter’s dependability.

Furthermore, standard SCMLI architecture frequently requires a significant number of capacitors to produce the appropriate output voltage levels, which complicates the design and increases the inverter’s overall size and cost. This is especially problematic in medium-voltage applications when space and weight are limited. As a result, the constraints inherent in SCMLI designs can hinder their practical application in medium voltage systems..

The proposed inverter is a potential solution to these issues. When compared to standard MLI topologies, the design uses a configuration with four capacitors and two bidirectional switches, reducing the total component count. This simplicity improves reliability while reducing potential points of failure. Additionally, the unique charging method of charging two capacitors to 1 VDC and two to 0.5 VDC allows for better voltage management and distribution. The configuration allows for smoother voltage transitions, which improves efficiency, as seen by the inverter’s performance of 98.4% at 120W and about 97.7% at 1.5 kW.

Furthermore, this arrangement can provide numerous output voltage levels using fewer components, making it ideal for medium voltage applications. The efficient regulation of voltage levels not only ensures stable operation under changing load conditions, but it also decreases the risk of thermal difficulties that are typically linked with high switching frequency. The suggested inverter’s ability to maintain high efficiency and good voltage regulation makes it a dependable choice for medium voltage systems.In comparison to other types of multilevel inverters, such as diode-clamped or cascaded H-bridge inverters, the suggested topology has advantages in medium voltage settings. Diode-clamped inverters frequently use many diodes and capacitors, increasing component count and complexity, but the suggested design only requires one diode. Although cascaded H-bridge inverters are modular, they still require significant space for many H-bridges and associated components, which might be a drawback in compact installations.

By facilitating effective energy conversion in microgrids, fuel cells play a crucial role in supplying sustainable energy solutions. Advanced controllers and inverters are required to manage power quality and stability in order to improve the operation of fuel cell-based microgrids. This fuel cell’s ability to separate energy conversion and management enables individual optimization for each microgrid function, including cost, performance, and other installation issues. This is one of its main advantages. The development of the suggested Advanced Energy Management (AEM) structure in14 focuses on two essential parts: a switched capacitor multilevel inverter (SCMLI) and a self-regulated controller (SRC).

A seven level SCMLI is proposed in14 which is utilized in the fuel cell and the high THD% of the SCMLI is mitigated by integrating the proposed SCMLI in the paper by AEM. The proposed ANPC topology provides a lower thd% of voltage harmonics. When LS-PWM is implemented on the proposed topology, it provides a THD% of 22.31%, similarly when PS-PWM is implemented on the proposed topology, it provides a THD% of 24% and when the proposed hybrid LS-PWM and PS-PWM is implemented on the proposed topology, it provides a THD% of 22.27% only, whereas, the SCMLI proposed in14 provides a THD% of 26.76% when LS-PWM is implemented. The proposed inverter when implemented with any three of the modulation schemes mentioned above provides a superior harmonic profile which makes it easier to integrate with AEM scheme. The SCMLI proposed in14 also has a higher component count, that is, it utilizes 11 switches (out of which one is bidirectional) and 2 capacitors. The ANPC proposed here has is less bulky comparatively as it utilizes 6 switches (out of which 2 are bidirectional), 4 capacitors and 2 diodes. The proposed ANPC also is highly efficient. Although the boosting provided is 1.5 and not triple boosting as provided by the SCMLI proposed in14, the voltage stresses in the components like switches and capacitors are low and thus provides higher efficiency.

The low THD% and high efficiency makes it suitable for use in the fuel cell systems described in14

Figure 2 shows charging and discharging of capacitors. CU1 and Cl1 are constantly being charged, to 1VDC, whereas CU2 and Cl2 are being charged and discharged in states 1.5, − 0.5, − 1 and 1, 0.5, − 1.5. In the same cycle all four capacitors are being charged and discharged and are thus self-balanced.

(a) + 1.5Vdc STATE (b) + 1Vdc STATE (c) 0.5Vdc STATE (d) 0Vdc STATE (e) 0Vdc STATE (f) − 0.5Vdc STATE (g) − 1Vdc STATE (h) -1.5Vdc STATE.

Therefore, (i) by suitable selection of capacitors size, (ii) by charging the capacitors in series and discharging in parallel and (iii) by maintaining duration of charging-discharging within one full cycle, capacitors used in the proposed ANPC MLI are said to be self-balanced. Therefore, additional voltage balancing control as required in conventional flying capacitor circuit is undesired. It is clear from the operational analysis that capacitors supply power to the load. Therefore, the voltage ripple should be limited to a low value. The voltage ripple and the voltage balancing depend on suitable value of capacitance, total discharging period within a cycle and loading in the circuit. To maintain the total power loss low, the voltage ripples should be kept within a limit. The capacitor CU1 is charged in the duration [t1, t2] and [t3, t4], while it discharges during [t2, t3]. In a similar way, both CU2 and Cl2 discharges during [t3, π-t3]. Considering this, the maximum discharging quantity of any capacitor can be expressed as15:

where ilp is the peak load current and tx & ty denotes the instant of discharging duration. As the peak load voltage is 1.5 Vin and assuming the load impedance of Zo, (1) can be further simplifies as15:

The discharging quantity can also be calculated as ΔQ = C*ΔVr and thus the minimum capacitance can be determined as follows15:

where ΔVr is the voltage ripple that can be expressed as δVin considering ripple factor of δ%. It is clear from (3) that capacitance varies with respect to the ripple % and load power factor. It can be concluded that if the ripple factor of input DC voltage is high then the power factor magnitude is low which means the efficiency goes low.

Figure 2 depicts the various switching modes of the proposed inverter to illustrate its operating principle. Capacitors CU1 and Cl2 are charged to 0.5Vdc through which S1 and S2 are charged to the same. Similarly, CU2 and Cl2 are charged to 1Vdc, charging S3 and S4 to the same. Sb6 is a bidirectional switch which allows the current to flow in either direction allowing to generate ± 1Vdc level when S3 or S4 is switched ON. Sb5 is also a bidirectional switch (considering D3, D4, D5 and D6 together with a unidirectional switch) which generates a 0 Vdc level. + 1.5Vdc level can be generated when S1 and S3 are turned ON whereas − 1.5Vdc can be generated when S2 and S4 are turned ON. Similarly, when S1 and S4 are turned on, a + 0.5Vdc level is generated and when S2 and S3 are switched ON, a − 0.5Vdc level is generated. Sb6 is also a bidirectional switch (considering two switches are connected in an anti-parallel way). Table 1 represents the switching states of the switches and diodes.

According to Table 1 and Fig. 2b, 0.5 Vdc is developed at the output by turning ON S2 and S3. In this state, the upper capacitor of the second leg is charged through the input DC source, D1, and S2 (D2 is in reverse bias, so it is turned OFF). Figure 2a,h show the development of ± 1.5Vdc. The leg is charged through D2. Figure 2b,g shows the development of ± 1Vdc. Figure 2d,e show the two paths for developing the 0Vdc level. Figure 2c,f show the development of level ± 0.5Vdc. In Fig. 2, red dashed lines show the charging path of capacitors CU2 and Cl2, while the blue dashed lines show the charging path of capacitors CU1 and Cl1 and the blue coloured path of the circuit shows the flow of current.

LS-PWM and PS-PWM are combined in the proposed modulation method. This methodology incorporates six carrier waveforms and one sine waveform. Here the first two carrier waves with maximum amplitude set as 1.5 and minimum as 1 are in phase shift form with respect to each other. Similarly, the carrier waveforms 5 and 6 are also in phase shift form with respect to each other. The waveforms 3 and 4 are in level shift form with respect to each other. All the 3 sets of waveforms (1 and 2, 3 and 4, 5 and 6) are level-shifted with respect to the other, all with reference to a single sine waveform. Figure 3 shows the circuit diagram of the proposed modulation scheme. Figure 4 shows the proposed hybrid of LS PWM and PS PWM, LS PWM and PS PWM. The proposed modulation technique reduces the charging current of the capacitors to a good extent, thus resulting in reduced losses. This can be seen in Figs. 20 and 21, in section "Simulation and experimental results".

Circuit diagram of the proposed modulation scheme.

(a) Proposed Modulation Technique– HYBRID of LS- PWM and PS-PWM (frequency = 1 kHz) (b) LS-PWM (c) PS-PWM.

Further, the section discusses the analysis of average switching loss.

Figure 3 shows the logic circuit of the proposed modulation scheme. Carrier waves (CW) 1 and 2 have the maximum and minimum amplitudes as 1.5 and 1, carrier wave 2 is phase shifted with respect to carrier wave 1 by 180°. Similarly, carrier waves 5 and 6 have maximum and minimum amplitudes as − 1 and − 1.5, carrier wave 6 is phase shifted with respect to carrier wave 5 by 180°. The reference modulating signal is a sine wave. The modulating signal and the carrier waves are input to the comparator, which generates different levels for the output. The level signals are input to the switches of the proposed ANPC inverter according to the switching table.

The equations provided denote the following: i(t) represents the current traversing the switch; v(t) signifies the voltage across the switch; and Esw,on and Esw,off denote the switching energy losses incurred by the switch, respectively, during its turn-on and turn-off transition times.

With reference to, turn-on switching and turn-off switching losses are given by16:

In (6) and (7), Esw, on* and Esw, off* are the experimentally measured values of the transistor’s turn-on and turn-off energy losses. VCC and ICC are the peak turn-on and turn-off voltages and currents for the desired switched-on and switched-off state. VCC* and ICC* are the rated voltages and currents for transistor switches’ turn-on and turn-off energy losses; these are provided in the datasheets of the transistor switches.

Utilizing the method proposed in16, we calculate the average switching turn-on and turn-off losses of every switch.

The average switching turn-on power loss is given by16:

where,

T = period time considered,

Tp = period for a single pulse (here for ON state).

n = number of switching operations performed during time T.

Similarly, the average switching turn-off power loss is given by:

where,

T = period time considered,

Tp = period for a single pulse (here for OFF state).

n = the number of switching operations performed during time T.

where,

Psw = total average switching loss.

Tp is calculated utilizing the method mentioned in16, similarly, Eon(t) and Eoff(t) are also calculated using the parameters i(on)(t) and i(off)(t).

The switching signals applied to the gate of transistors are depicted in Fig. 5. Table 2 lists the various parameters utilized in calculating the average switching losses of each switch. The VCC for both turn-on and turn-off times is the same, as the pulse for each switch is rectangular. ICC,on and ICC,off are the turn-on and turn-off currents for a single pulse; we calculate these for up to n switching operations and calculate Psw with reference to16,17. After the above simplification, using MATLAB Simulink or PLECS, we can measure the time run for a single pulse for each switch and using the energy losses given in the data sheets the average switching losses can be calculated, though they do differ by small values in comparison to calculated values we got by using PLECS when performing power loss analysis due to many more loss and thermal factors. The above method mentioned is an approximate method of calculating switching losses.

(a) Switching signals for S1, S2 and S3 (b) Switching signals for S4 Sb5 and Sb6.

Comparison of proposed topology with other topologies is presented in Table 3. To facilitate a precise comparison, Table 3 lists the components required to construct the inverter topologies under consideration. The components such as capacitors, diodes, switches and their count, and the number of switch driver circuits play an important role in affecting the efficiency of the inverter. All such parameters are compared for different topologies and the proposed topology.

An important component that plays a crucial role and increases the complexity of an inverter is the number of switches. The topology discussed in18 consists of eight switches and 7 switch driver circuits, while the topology discussed in19 and20 has 12 switches with 7 switch driver circuits. The topology in proposed in21 utilizes 9 switches, 3 capacitors, 9 gate drives and 3 diodes. The inverter provides an efficiency of 97.9%, which is low when compared to the proposed and is also bulky comparatively. Meraj et al22 proposes a seven level inverter which utilizes 12 switches and 2 capacitors, providing a triple boosting which causes higher voltage stress and lower efficiency, that is, 94.8%. The proposed topology includes a higher number of diodes compared to existing topologies, but it does not include switch driver circuits, which enhances efficiency.

The quantity and design of components also have a significant impact on enhancing efficiency or decreasing switching losses. One of the main objectives of the design of the inverters is to reach higher voltage levels, boosting efficiency with a lower component count.

Table 3 additionally provides the component count. Inverters comprising a reduced number of components are expected to exhibit greater efficiency and cost-effectiveness. The capacitors are the second-weakest link in power electronic converters. The capacitor is responsible for a significant proportion of the inverter’s cost and volume, as well as its bulk. Therefore, reducing the capacitor count and its rating is essential. The topologies discussed in Table 3 mainly consist of lower capacitor counts, but each or at least one capacitor is rated at 2Vdc. The topology discussed with reference to18 has an overall lower component count but it has comparatively the highest capacitor count, and switch count leading to decreased efficiency. The proposed topology has a higher capacitor count comparatively but is low rated, 0.5Vdc and 1Vdc resulting in overall improved efficiency. Overall, the proposed inverter topology offers several advantages over the other topologies discussed.

Comparing the proposed seven level ANPC topology with several other multi-level topologies. Jena et al.23 presents a five level CGT which utilizes 10 switches and two capacitors. Pal et al.24 proposes a nine level SCMLI which provides an efficiency of 98.03% at 583W, the proposed topology, seven level, provides an efficiency of 98.22% at 500 W. One of the reasons for high efficiency is the low stress on the components as it provides lower boosting. Jena et al.25 proposes a nine level topology utilizing 12 switches and 3 capacitors providing the highest efficiency 96.8% at 200W, whereas the proposed ANPC topology utilizes 7 switches and 4 capacitors, provides 98.2% at 200W, the losses are reduced due to proposed LS-PS hybrid modulation scheme. The topology proposed in26 presents a five level SCMLI, which utilizes 10 switches. 2 capacitors and 1 diode. The proposed inverter is bulky for a five-level output, although it provides dual boost, the efficiency is 97.35, which is low in comparison to the proposed and other seven level MLIs. The topology proposed in27 is a nine-level inverter- pencil shaped. It utilizes 10 switches, out of which two are bidirectional, that is, it utilizes 12 power switches 2 capacitors and 2 DC sources, providing quadruple boosting, which leads to high voltage stress on the components – switches and capacitors and thus lower efficiency, that is, 95.5%. Neti et al.28 proposes a five-level inverter which provides no boosting, utilizes 6 switches and 2 capacitors and provides highest efficiency to be 97.6%. Meraj et al.29 proposes a nine-level inverter providing and efficiency of 95.54% and quadruple boosting. It utilizes 10 switches, 4 capacitors and 4 diodes, providing higher voltage stress due to quadruple boosting and thus lower efficiency comparatively. Anand et al.30 proposes a nineteen-level inverter providing an efficiency of 94.42% at 500 W. As it provides 19 levels, the inverter is bulky and voltage stress on components is high leading to low efficiency. Anand and Singh31 proposes a thirteen-level inverter which utilizes 14 switches and 3 capacitors with highest attained efficiency of 97.5%. It also utilizes 15 gate drivers. Anand et al.32 proposes a five-level inverter, providing dual boosting which utilizes 8 switches and 2 capacitors providing an efficiency of 97.2% at 900W. The proposed inverter is bulky for providing five levels and provides lesser efficiency comparatively, that is, proposed ANPC provides an efficiency of 98.1% at 900W. One of the major reasoning is the boosting, as the proposed ANPC inverter provides only 1.5 whereas the inverter proposed in32 provides dual boosting, leading to higher voltage stresses. The topology proposed in13 provides seventeen-level output, providing a 8 time boosting, utilizing 12 switches, 4 capacitors, 5 diodes and 12 gate drivers and efficiency of 95.4% at 1 kW. Anand et al.33 proposes a five level inverter which utilizes 8 switches and 2 capacitors providing the highest attained efficiency of 96.2%

This section compares the outcomes obtained with LS-PWM and PS-PWM with a few parameters of the suggested PWM approach. Figure 6 compares the THD% and efficiency of LS-PWM and PS-PWM and the proposed PWM. The proposed technique results in comparatively fewer distortions. Figures 13, 14 and 15 in section "Simulation results" show the THD% graphs for all three modulation techniques. Figure 6a compares the THD% of voltage harmonics, Fig. 6b compares the THD% of current harmonics while 6(c) compares efficiency.

(a) Radar plot of v thd(%) (b) Radar plot of I thd(%) (c) Radar plot of efficiency.

Figure 6c shows the highest efficiency achieved using the three techniques. PLECS software is used for implementing the three modulation techniques and finding out the efficiency and losses. Switching and conduction losses are also compared to ensure a fair comparison. By implementing the topology and modulation techniques in PLECS, these losses are computed. Figure 6c presents the maximum efficiency that was attained through the implementation of the three techniques. In order to implement the three modulation techniques and determine their losses and efficiencies, the PLECS software is utilized. Switching and conduction losses are also compared to ensure a fair comparison. By implementing the topology and modulation techniques in PLECS, these losses are computed.

Figure 7 shows the radar plots of switching and conduction losses of each switch under load 450W utilizing the three modulation techniques. LS-PWM, PS-PWM and LS-PS HYBRID PWM. These values are calculated using PLECS software. The correlation between PS-PWM and increased switching and conduction losses is indisputable, while LS-PWM exhibits a notably diminished influence on these variables. The suggested modulation method effectively lowers large conduction losses; switching losses are only slightly higher than LS-PWM, but still a lot lower than PS-PWM. Significant reductions in conduction losses result in improved efficiency and overall loss minimization.

(a) Radar plot for switching loss at each switch utilizing the three modulation techniques (b) Radar plot for conduction loss at each switch utilizing the three modulation techniques.

Power losses are evaluated utilizing PLECS 4.8. Power losses within an inverter can be attributed to various factors, including conduction, and switching losses caused by other inverter components, such as diodes and capacitors. The entire power loss analysis has been performed on circuit simulated in PLECS 4.8.

The assessment of power loss is paramount in guaranteeing dependable, cost-effective, and efficient functioning. The system operates more cost-effectively when losses are reduced.

This section will provide a detailed explanation of the factors that were evaluated using the PLECS software, including power losses, efficiency, and others.

The complete analysis is done by taking into consideration only the losses of the switches.

The varying losses incurred by each switch utilizing hybrid LS-PS-PWM are presented in Fig. 6 above.

The components and their values utilized in the analysis of the converter’s topology are detailed in Table 434. The analysis of loss at various loads is illustrated in Fig. 835.

(a) Efficiency vs Power curve comparing LS-PWM, PS-PWM and LS-PS PWM (b) Efficiency vs Power curve for LS-PS PWM.

Figure 8 shows the power efficiency curve at different loads. As load and power increase, initially, the efficiency increases to a certain point, and then it starts to fall. Efficiency is one of the most important parameters for the analysis and application of an inverter. In Fig. 6c, we have also compared the efficiency of different techniques implemented of inverters, with the proposed topology having the highest efficiency comparatively.

As illustrated in Fig. 9, an increase in load results in a corresponding rise in conduction losses.

Switching and conduction losses (out of total power loss) at different loads.

As shown in Fig. 8, the maximum efficacy attained is 98.4%, under 120W.

The efficiency of the inverter here is calculated considering switching losses only. Figure 10 shows the simulation model build in PLECS 4.8 for power loss analysis considering the losses of switches only.

Efficiency of the inverter considering the losses of switches only calculated using PLECS.

Figure 9 shows the comparison of switching and conduction losses for loads 120 W, 450 W and 1200 W. As we increase the loads, the switching losses decrease for all three modulation techniques. It can be observed that the switching losses for LS-PWM are comparatively slightly lower compared to LS-PS Hybrid PWM though conduction losses are reduced to a good extent comparatively. In comparison to PS-PWM, the switching losses have been reduced to a good extent. It is overall observed that even though LS-PWM has slightly lower switching losses it has higher conduction losses, for PS-PWM, conduction losses are less but switching losses are higher. The proposed modulation technique utilizing the benefits of both the PWMs, it has reduced switching and conduction losses when compared to PS-PWM and LS-PWM.

The efficiency of the proposed topology considering capacitor losses under 120W is 97.78, shown in Fig. 11.

Efficiency of the inverter considering the losses of switches and capacitors calculated using PLECS.

The function [f(n)] used for calculating the efficiency in PLECS is as follows in Eq. (13):

where, u1 is the total loss and u2 is the input.

Switching transition occurs during operation of the MLI. The speed of switching and the loss depends on the internal capacitance of the switches. This capacitance increases and decreases when transition of the switch occurs from off state to on state. In other words, the internal capacitor (Cn) charges and discharges during the switching transition. Further, considering the switches are required to withstand a voltage stress (Vn) when in the off condition, the energy loss can be determined as follows15:

Further, considering the N average number of switching transitions (depending on the switching time) in a switching cycle and the nominal frequency as fn, the total switching power loss for the nine switches becomes15:

Conduction loss occurs due to the consideration of parasitic parameters such as the internal resistance and equivalent series resistance of the switches and diodes. The total parasitic resistance can be evaluated by considering the number of switches and diodes conduct in each instant from t0 – t4. For instance, during zero-level the load current (io) flows through one switch, which results in total parasitic resistance (Req0) of Rs. Similarly, considering the load current path in ± 0.5Vin, ± 1Vin, and ± 1.5Vin level, the total parasitic resistances in each level are (Req1, Req2, Req3) 2Rs + Rd, 1Rs + Rc, and 1Rs + Rc; where Rs, Rd, and Rc are the on-state resistance of the switch, on-state resistance of the diode and internal resistance of the capacitor, respectively. Considering forward voltage drop of diode Vd, the conduction energy loss and total conduction loss are expressed in (16) & (17), respectively 15.

The capacitors are charged in parallel and let us consider the capacitor CU1, which is charged in parallel with the dc source. Practically during charging, a potential difference exists between the input voltage magnitude and the capacitor voltage magnitude. This causes voltage ripple that is expressed as follows15:

The total ripple loss becomes:

Thus, the total efficiency of the proposed ANPC MLI is calculated as:

The total power loss of switches is obtained as follows34:

The power losses of the switches in the first, second, third and fourth switch legs are denoted as ΔPhbt1, ΔPhbt2, ΔPhbt3, and ΔPhbt4 respectively.

The expression for the power loss of a diode is:

The variables Tch, vsd, ich(t), Rdn, fsw, and Edoff show how long it takes for the diode to charge, the ON-state reverse voltage of the diode, instantaneous current, ON-state resistance of the diode, and the wasted energy due to the reverse recovery stage of the diode.

The power losses of the nth capacitor due to ESR is given as34:

The total power loss of the proposed inverter is given as follows:

The consistency, dependability, and stability of a measurement instrument or system are evaluated through the utilization of reliability analysis. Reliability analysis is employed by researchers and practitioners to ascertain the consistency and dependability of the instruments within their use. An indicator of high reliability is the consistency and dependability of the measuring instrument. The stability and effectiveness of these systems as a whole are dependent on the reliability of inverters. Reliability is conceptualized as the likelihood that an apparatus will execute its designated functionalities (commutation, on-state, and off-state) for a designated duration during typical operation, provided that the apparatus operates within its designated safe operating zone. The Markov approach is one of the most widely used methods for assessing the dependability of systems. Markov chains are widely used for reliability analysis due to their ability to model systems with probabilistic state transitions over time. The Markov chain method involves utilizing Markov models to represent the system under study. This typically involves defining different states that the system can be in (e.g., healthy, faulty, failure) and determining the probabilities of transitioning between these states. The Markov chain diagram of the proposed inverter is given in Fig. 12. The inverter assumes three states, denoted as p1, p2, and p3. The state p1 denotes the healthy state in which all components are deemed to be in good condition; p2 signifies the faulty state in which the inverter fails to produce any waveform levels due to the failure of one or two components; and p3 signifies the failure state in which the output fails to generate any waveform levels36. The mathematical definition of the following is possible using P1(t), P2(t), and ƛx, which represent the occupational probability of the state p1 and the failure rate of the element x, respectively:

MARKOV CHAIN.

The reliability of the proposed inverter can be written as:

The failure rate of each component of each component can be defined as:

The symbol λb represents the base failure rate of the component, which is 0.012 for the switch and 0.00254 for the capacitor36. The variable n represents the number of α factors that impact the failure rate of component x. These factors include temperature (αT), quality (αQ), application (αA), and environment (αE). As a result, the subsequent data delineates the rates at which a switch (λS) and capacitor (λC) fail):

In the process of determining reliability, it is assumed that the semiconductor device is in an ideal condition; thus, αQ = αA = 1. Moreover, αE = 1 can be chosen under the assumption that all components function in an identical environment. All factors, with the exception of αT, are assumed to remain constant36. The computation of αT for a semiconductor switch is as follows:

where Tj is the device junction temperature and is determined using the following relations:

The variables denoted as Ta, θca, θjc and Ploss are as follows: θjc represents the thermal impedance of the switch, which is assumed to be 0.45 °C/W; θca represents the case-to-ambient thermal impedance, which is 62/W; Ta is assumed to 25 °C 36and Ploss signifies the overall power loss incurred by the switch. The computation of the capacitance factor αCV and stress factor αS for the capacitor is as follows:

In this context, Vs represents the operating voltage to rated voltage ratio, while C denotes the capacitance measured in microfarads. A comprehensive thermal analysis of the inverter topology under consideration is conducted utilizing PLECS. Table 5 shows power losses obtained in PLECS, \({\boldsymbol{\alpha }}_{{\varvec{T}}}^{{\varvec{s}}{\varvec{w}}{\varvec{i}}{\varvec{t}}{\varvec{c}}{\varvec{h}}}\) and \({{\varvec{\lambda}}}_{{\varvec{s}}{\varvec{i}}}\) of the switches in a healthy state.

With reference to the Markov chain in Fig. 12, the corresponding probabilities are calculated as:

Tables 6 and 7 shows power loss, \({\boldsymbol{\alpha }}_{{\varvec{T}}}^{{\varvec{s}}{\varvec{w}}{\varvec{i}}{\varvec{t}}{\varvec{c}}{\varvec{h}}}\) and \({{\varvec{\lambda}}}_{{\varvec{s}}{\varvec{i}}\boldsymbol{ }}\) in fault states.

\(\left[{\varvec{A}}\right]\) is the matrix in which all the values are calculated considering the switches state transfer i.e. from failure to fault state, healthy to failure state and fault to failure state. All these states are considered for all switches and for all possible combinations of two switches, failing together.

The final \(\left[{\varvec{A}}\right]\) is as follows:

The resulting equations are as follows:

In this section, the performance parameters of the proposed inverter are evaluated through the execution of a laboratory-built experiment and a MATLAB/Simulink 2024b model. The integration of the proposed inverter with the PV unit through a PI controller is implemented in the simulation model. A locally accessible load is utilized throughout the experiment to assess the efficacy of the proposed inverter and modulation technique.

The proposed inverter has been simulated using PS-PWM, LS-PWM, and a hybrid LS-PS-PWM for the sake of clarity.

A simulation of the three modulation techniques and their THD (%) is shown in Figs. 13, 14, and 15. Figure 13a shows the current and voltage waveforms when simulated while employing LS-PWM and Fig. 13b,c show the THD of the voltage and current waveforms. Similarly, Fig. 14 shows the waveforms and THD when PS-PWM is employed, while Fig. 15 shows the waveforms and THD when employed with the proposed modulation technique on RL load R = 100 Ω and L = 120 mH.

Waveforms and THD (%) when LS-PWM is employed (a) Output Voltage and Current waveforms (RL Load) (b) Output Voltage and Current waveforms (R Load) (c) THD % in voltage waveforms (d) THD% in current waveforms.

Waveforms and THD (%) when PS-PWM is employed (a) Output Voltage and Current waveforms (RL Load) (b) Output Voltage and Current waveforms (R Load) (c) THD % in voltage waveforms (d) THD% in current waveforms.

Waveforms and THD (%) when HYBRID LS-PS-PWM is employed (a) Output Voltage and Current waveforms (RL Load) (b) Output Voltage and Current waveforms (R Load) (c) THD % in voltage waveforms (d) THD% in current waveforms.

Figure 16 shows the output current and Voltage waveforms on R Load (R = 100 Ω) and RL Load (R = 100 Ω, L = 120 mH).

(a) R = 100 Ω (b) R = 100 Ω, L = 120 mH.

Figure 17 shows the current waveforms when the R load changes during simulation. It is clear from the results that as the load decreases, so does the current amplitude and as it increases, the current amplitude also increases. Figure 18 shows the current waveforms when the RL load changes, it becomes clear from the results that current and load changes are proportional to each other, following the same pattern as the R load.

(a) R load decreases, (b) R load increases.

(a) RL load decreases (b) RL load increases.

Figure 19 shows the voltage and current waveforms when the modulation index changes during simulation.

(a) Modulation index decreases (b) Modulation index increases.

Figures 20 and 21 show the voltage and current through capacitor CU2 Cl2. CU1 and Cl1 utilizing modulation techniques LS-PWM, PS PWM and LS-PS Hybrid PWM. All are taken on R = 40 Ω and L = 120 mH. It can be observed from the figures that in comparison to LS PWM, PS PWM and LS-PS HYBRID PWM, the charging current through the capacitors while utilizing LS-PS HYBRID PWM has decreased significantly in all the capacitors, thus contributing. Table 8 shows the parameters used for simulation.

(a) Current passing through capacitor CU2 using LS-PS HYBRID PWM (b) Current passing through capacitor CU2 using LS PWM (c) Current passing through capacitor CU2 using PS PWM (d) Current passing through capacitor Cl2 using LS-PS HYBRID PWM (e) Current passing through capacitor Cl2 using LS PWM (f) Current passing through capacitor Cl2 using PS PWM.

(a) Current passing through capacitor CU1 using LS-PS HYBRID PWM (b) Current passing through capacitor CU1 using LS PWM (c) Current passing through capacitor CU1 using PS PWM (d) Current passing through capacitor Cl1 using LS-PS HYBRID PWM (e) Current passing through capacitor Cl1 using LS PWM (f) Current passing through capacitor Cl1 using PS PWM.

An experimental setup is utilized to assess the proposed topology in this section. The outcomes of the suggested topology are validated through an experimental configuration conducted within the laboratory.

Experimentally observed voltage and current waveforms under R load and RL load, where R = 40 Ω and L = 120 mH, are depicted in Fig. 22a, b.

Voltage and Current waveforms (a) RL Load- R = 40 Ω, L = 120 mH (b) R Load Input Voltage = 50 V, 36V/division.

A seven-level stepped waveform is generated at power factor unity for voltage at both R load and RL load, whereas a sinusoidal wave is generated for RL load and a stepped seven level is generated for current at R load.

Figure 23 shows the voltage and current through the capacitor (Cl2) validating the simulation results obtained.

Voltage and current through capacitors (Cl2) 5A/division.

Figure 24 shows the waveforms when the load is switched from R load to RL load and when the load is being switched from RL load to R load. This shows that the inverter works for both kinds of load even when the load is being switched simultaneously.

RL load to R load Input Voltage = 50 V, 36V/division.

Figure 25 shows the waveforms when the frequency is switched from 50 to 100 Hz at power factor unity. This shows the capability of the inverter to work accurately at different frequencies.

The frequency is being switched from 50 to 100 Hz. Input Voltage = 50 V, 25 V/division

Figure 26 shows the voltage and current waveforms when the modulation index decreases from 1 to 0.7. This shows a reduction in levels in voltage stepped waveform, from seven to five levels and a change in amplitude of the current sinusoidal waveform.

Modulation index decreases from 1 to 0.7

Furthermore, Fig. 27a,b show the harmonic spectrum of voltage and current waveforms. This shows a waveform with comparatively lower THD just as shown in simulation results.

(a) Harmonic spectrum for voltage waveform, THD (%) = 22.27 (b) Harmonic spectrum for current waveform THD (%) = 10.67.

All the results are taken for load R = 40 Ω and L = 120m H. The above results show the accuracy and efficiency of the proposed topology and the modulation scheme. All the results are taken for the proposed modulation scheme implemented on the proposed topology, hence validating its working and efficiency.

Table 9 shows the different parameters used when taking simulation and experimental results.

In this article, a single phase seven level active neutral point clamped inverter is proposed. The proposed topology boosts the voltage up to 1.5 VDC, resulting in the output voltage having seven levels. The inverter utilizes four capacitors, six diodes and seven switches. Although its boost is limited to 1.5 VDC, due to lower voltage stresses on switches and capacitors its efficiency is high. It is also proposed and evident through simulation and experimental results that the hybrid of LS-PWM and PS-PWM when implemented on the proposed topology would lead to lower losses, and higher efficiency compared to LS-PWM, PS-PWM, and other topologies. The efficiency is increased up to 98.4%, the capacitor charging currents are reduced significantly, evident through simulation results, contributing to reducing losses. The THD% of the voltage and current harmonics is 22.27% and 10.67%. The proposed ANPC seven-level inverter has high potential for use in renewable energy systems, electric cars, and grid-tied systems. Its multi-level design reduces harmonic distortion and switching losses, making it suitable for solar systems, wind energy conversion, and battery energy storage. In electric vehicles, it can function as an efficient inverter for traction systems and on-board chargers. For industrial drives and medium-to-high voltage applications, it improves motor efficiency while decreasing heat stress on components. The proposed inverter is shown to be workable through simulations, experimental tests, and an analysis of power loss in PLECS.

The datasets used and/or analysed during the current study available from the corresponding author on reasonable request.

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The authors extend their appreciation to King Saud University for funding this work through Researchers Supporting Project number (RSP2025R387), King Saud University, Riyadh, Saudi Arabia. The authors would also like to acknowledge the facilities provided by Non-Conventional Energy Lab, Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India for carrying out the research work.

Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh, 202002, India

Bisma Saif, Adil Sarwar & Mohammad Zaid

Industrial Engineering Department, College of Engineering, King Saud University, 11421, Riyadh, Saudi Arabia

Shafiq Ahmad

Undergraduate Program of Vehicle and Energy Engineering, National Taiwan Normal University, Taipei, 106, Taiwan

Hwa-Dong Liu & Wei-Jen Chen

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B.S. carried out the experiment B.S. wrote the manuscript with support from A.S., M. Z., S.A., H.D., and W.C.

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Saif, B., Sarwar, A., Zaid, M. et al. A single-phase seven-level ANPC inverter with hybrid modulation for enhanced efficiency and harmonic performance. Sci Rep 15, 9551 (2025). https://doi.org/10.1038/s41598-025-93660-8

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Received: 25 October 2024

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DOI: https://doi.org/10.1038/s41598-025-93660-8

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